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Page 16 of 27

Senior Staff DFT Engineer·Marvell·Petah-Tikva
GPTVLSIDFTEDASilicon
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Senior Staff System & Modeling Engineer – Wireline Communications·Marvell·Santa Clara, CA
PythonMATLABVerilogGPT
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DSP Architecture System Modeling Engineer·Marvell·US-NY - Hudson Valley
PythonC++PandasNumPyGPTGitHub
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Staff Engineer, Analog Layout·Marvell·Hsinchu City
GPT
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Sr. Staff Engineer, Hardware Design·Marvell·Taipei
GPTCadence
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Sr. Staff Engineer, Analog IC Design·Marvell·Hsinchu City
MATLABVerilogGPTCMOS
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Principal Engineer, Analog IC Design·Marvell·Hsinchu City
MATLABVerilogGPTCMOS
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Software Development Engineer (ARM, RISC, Crypto, HSM)·Marvell·IN - BangaloreHybrid
GPTLinuxSystem DesignFPGAASIC
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Director for Design Verification·Marvell·Santa Clara, CA
GPTASICUVMSilicon
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SYN/STA Engineering Intern (Optical PHY)·Marvell·Ho Chi Minh
PythonGPTASICRTLEDASynopsys
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SYN/STA Engineer Intern (CCS)·Marvell·Ho Chi Minh
PythonVerilogGPTLinux
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Software/Firmware Engineering Intern·Marvell·Ho Chi Minh
PythonGPT
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Engineering Project Management Intern (Connectivity)·Marvell·Ho Chi Minh
GPT
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Engineering Project Management Intern (AMS COMPHY)·Marvell·Ho Chi Minh
GPTSilicon
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Physical Design Engineer Intern·Marvell·Ho Chi Minh
GPTSynopsysCadence
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Emulation Intern·Marvell·Ho Chi Minh
PythonBashVerilogGPTLinuxSilicon
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Digital IC Design Intern (Connectivity)·Marvell·Ho Chi Minh
MATLABVerilogGPTLinuxASIC
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Digital IC Design Intern (AMS COMPHY)·Marvell·Ho Chi Minh
BashMATLABVerilogGPTASICTCL
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Design-for-Test (DFT) Engineering Intern·Marvell·Ho Chi Minh
VerilogGPTLinuxASICEDA
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Design Verification Intern (Connectivity)·Marvell·Ho Chi Minh
VerilogGPTLinux
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Design Verification Intern (CCS)·Marvell·Ho Chi Minh
VerilogGPTLinuxUVM
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Analog Layout Intern·Marvell·Ho Chi Minh
GPTEDA
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Analog IC Design Intern (Optical PHY)·Marvell·Ho Chi Minh
PythonMATLABGPTCadence
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Analog IC Design Intern (COMPHY)·Marvell·Ho Chi Minh
GPT
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Design Verification, Manager·Marvell·Ho Chi Minh
VerilogGPTUVM
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