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Page 17 of 27

Principal Engineer, RTL ASIC Design·Marvell·Bangalore
PythonVerilogGPTASICRTLSilicon
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Analog Layout Staff Engineer·Marvell·Bangalore
GPTCMOSEDATCLCadence
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System Design and Silicon Validation Intern (Connectivity)·Marvell·Ho Chi Minh
PythonMATLABGPTSystem DesignFirmwareSilicon
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Hardware Validation Intern·Marvell·Ho Chi Minh
PythonMATLABGPTSilicon
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Senior Staff Engineer - Analog IC Design·Marvell·Bangalore
GPTCMOS
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Senior Staff Field Application Engineer - Connectivity·Marvell·Santa Clara, CA
PythonGPT
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Director, SOC Design·Marvell·Santa Clara, CA
PythonGPTRTLTapeoutHBMDFT
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Silicon Photonics Validation Engineer·Marvell·Santa Clara, CA
GPTSystem DesignASICFirmware
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Staff Software & AI Engineer·Marvell·Yokneam
PythonC#PyTorchTensorFlowscikit-learnGPT
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SerDes Validation Senior Staff Engineer·Marvell·Santa Clara, CA
PythonGPTSilicon
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Senior Staff Applications Engineer·Marvell·Santa Clara, CA
GPTSystem DesignEDASynopsysCadence
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Principal Applications Engineer·Marvell·Santa Clara, CA
GPTSystem DesignEDASynopsysCadence
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Senior Principal Hardware Validation·Marvell·Santa Clara, CA
PythonGPTASICHBMFirmwareSilicon
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Senior Principal Engineer, RTL ASIC Design·Marvell·Bangalore
PythonVerilogGPTASICRTLSilicon
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Advanced Packaging Technology Pathfinding and Development Engineer·Marvell·Austin, TX
GPTHPCCadence
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Advanced Packaging Technology Pathfinding and Development Engineer·Marvell·Austin, TX
GPTHPCCadence
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Optical Engineer, Senior Staff·Marvell·Santa Clara, CA
GPTSystem DesignASICTapeoutCMOSFirmware
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Memory Layout Principal Engineer·Marvell·Bangalore
PythonGPTTapeout
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Validation Engineer (L1, L2, L3 Testing, NOS/SDK testing, Python Automation)·Marvell·Bangalore
PythonGPTGitHubFirmware
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Sr Benefits Operations Specialist – Americas·Marvell·Irvine, CA
GPT
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Senior Principal Software Applications Engineer·Marvell·Santa Clara, CA
GPTLinuxVLSIFirmware
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Package Development, Signal Integrity and Power Integrity Engineer, Staff·Marvell·Austin, TX
MATLABGPTCadence
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Principal Hardware Engineer - Board‑level system design - infrastructure/storage/network/PCIe Gen 5+/DDR4/5/Ethernet·Marvell·Irvine, CA
GPTLinuxASICCadence
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Principal Embedded Firmware Software Engineer - Networking PAM4 DSP/data center/AI connectivity·Marvell·Santa Clara, CA
PythonGPTSilicon
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Sr Staff Engineer, Design Verification·Marvell·Pune
VerilogGPTFirmwareUVMSilicon
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